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ST92195B
32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
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Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes 0C to +70C operating temperature range Up to 24 MHz. operation @ 5V10% Min. instruction cycle time: 165ns at 24 MHz. 32, 48, 56 or 64 Kbytes ROM 256 bytes RAM of Register file (accumulators or index registers) 256 bytes of on-chip static RAM 2, 6 or 8 Kbytes of TDSRAM (Teletext and Display Storage RAM) 28 fully programmable I/O pins Serial Peripheral Interface Flexible Clock controller for OSD, Data Slicer and Core clocks running from a single low frequency external crystal. Enhanced display controller with 26 rows of 40/80 characters - Serial and Parallel attributes - 10x10 dot matrix, 512 ROM characters, definable by user - 4/3 and 16/9 supported in 50/60Hz and 100/ 120 Hz mode - Rounding, fringe, double width, double height, scrolling, cursor, full background color, halfintensity color, translucency and half-tone modes Teletext unit, including Data Slicer, Acquisition Unit and up to 8 Kbytes RAM for data storage VPS and Wide Screen Signalling slicer (on some devices) Integrated Sync Extractor and Sync Controller 14-bit Voltage Synthesis for tuning reference voltage Up to 6 external interrupts plus one NonMaskable Interrupt 8 x 8-bit programmable PWM outputs with 5V open-drain or push-pull capability 16-bit watchdog timer with 8-bit prescaler One 16-bit standard timer with 8-bit prescaler 4-channel A/D converter; 5-bit guaranteed
PSDIP56
TQFP64
See end of document for ordering information
Rich instruction set and 14 addressing modes Versatile development tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and hardware emulators with Real-Time Operating System available from third parties s Pin-compatible EPROM and OTP devices available Device Summary
s s
Device ST92195B1 ST92195B2 ST92195B3 ST92195B4 ST92195B5 ST92195B6 ST92195B7 ST92T195B7 ST92E195B7
Program Memory 32K ROM 32K ROM 32K ROM 48K ROM 48K ROM 56K ROM 64K ROM 64K OTP 64K EPROM
TDS VPS/ RAM WSS 2K 6K 6K 6K 8K 8K 8K 8K 8K Yes No Yes Yes Yes Yes Yes Yes Yes
Package
PSDIP56/ TQFP64
CSDIP56 /CQFP64
Rev. 2.5
January 2000 1/22
1
ST92195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST92195B microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast context switching and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The ST92195B MCU supports low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File and the Interrupt controller. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. Two basic addressable spaces are available: the Memory space and the Register File, which includes the control and status registers of the onchip peripherals. 1.1.2 Power Saving Modes To optimize performance versus power consumption, a range of operating modes can be dynamically selected. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequency programmable via the CCU. In this mode, the power consumption of the device can be reduced by more than 95% (Low power WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode. 1.1.3 I/O Ports Up to 28 I/O lines are dedicated to digital Input/ Output. These lines are grouped into up to five I/O Ports and can be configured on a bit basis under software control to provide timing, status signals, timer and output, analog inputs, external interrupts and serial or parallel I/O. 1.1.4 TV Peripherals A set of on-chip peripherals form a complete system for TV set and VCR applications: - Voltage Synthesis - VPS/WSS Slicer - Teletext Slicer - Teletext Display RAM - OSD 1.1.5 On Screen Display The human interface is provided by the On Screen Display module, this can produce up to 26 lines of up to 80 characters from a ROM defined 512 character set. The character resolution is 10x10 dot. Four character sizes are supported. Serial attributes allow the user to select foreground and background colors, character size and fringe background. Parallel attributes can be used to select additional foreground and background colors and underline on a character by character basis. 1.1.6 Teletext and Display Storage RAM The internal Teletext and Display storage RAM can be used to store Teletext pages as well as Display parameters.
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ST92195B - GENERAL DESCRIPTION
INTRODUCTION (Cont'd) 1.1.7 Teletext, VPS and WSS Data Slicers The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS and WSS information from the video signal. Hardware Hamming decoding is provided. 1.1.8 Voltage Synthesis Tuning Control 14-bit Voltage Synthesis using the PWM (Pulse Width Modulation)/BRM (Bit Rate Modulation) technique can be used to generate tuning voltages for TV set applications. The tuning voltage is output on one of two separate output pins. 1.1.9 PWM Output Control of TV settings can be made with up to eight 8-bit PWM outputs, with a maximum frequency of 23,437Hz at 8-bit resolution (INTCLK = 12 MHz). Low resolutions with higher frequency operation can be programmed.
1.1.10 Serial Peripheral Interface (SPI) The SPI bus is used to communicate with external devices via the SPI, or I C bus communication standards. The SPI uses a single data line for data input and output. A second line is used for a synchronous clock signal. 1.1.11 Standard Timer (STIM) The ST92195B has one Standard Timer (STIM0) that includes a programmable 16-bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes. 1.1.12 Analog/Digital Converter (ADC) In addition there is a 4-channel Analog to Digital Converter with integral sample and hold, fast 5.75s conversion time and 6-bit guaranteed resolution.
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ST92195B - GENERAL DESCRIPTION
INTRODUCTION (Cont'd) Figure 1. ST92195B Block Diagram
Up to 64 Kbytes ROM 256 bytes RAM Up to 8 Kbytes TRI TDSRAM MEMORY BUS I/O PORT 0
8
P0[7:0]
I/O PORT 2 I/O PORT 3 I/O PORT 4
6
P2[5:0]
4
P3[7:4]
256 bytes Register File 8/16-bit CPU
8
P4[7:0]
I/O PORT 5 DATA SLICER & ACQUISITIO N UNIT SYNC. EXTRACTION REGISTER BUS VPS/WSS DATA SLICER ADC
2
P5[1:0]
NMI INT[7:4] INT2 INT0
MMU Interrupt Management ST9+ CORE TXCF CVBS1
OSCIN OSCOUT RESET RESETO
RCCU 16-BIT TIMER/ WATCHDOG
WSCR WSCF CVBS2
SDO/SDI SCK
SPI
AIN[4:1] EXTRG
VSYNC HSYNC/CSYNC CSO FREQ. PXFM MULTIP. R/G/B/FB TSLU HT
MCFM
TIMING AND CLOCK CTRL STANDARD TIMER
SYNC CONTROL ON SCREEN DISPLAY PWM D/A CONVERTER
STOUT
VSO[2:1]
VOLTAGE SYNTHESIS
PWM[7:0]
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
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ST92195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION Figure 2. 64-Pin Package Pin-Out
VDD P0.3 P0.4 P0.5 P0.6 P0.7 RESET P2.0/INT7 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT VDD GND AIN4/P0.2 P0.1 P0.0 CSO/RESET0/P3.7 P3.6 P3.5 P3.4 B G R FB SDO/SDI/P5.1 INT2/SCK/P5.0 VDD JTDO 1 64 48 16 32 VSS P4.7/PWM7/EXTRG/STOUT P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRST0 GND N.C.
N.C. = Not connected
N.C. N.C. WSCF VPP/WSCR AVDD3 TEST0 MCFM JTCK TXCF CVBSO AVDD2 JTMS CVBS2 CVBS1 AGND N.C.
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) RESET Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. R/G/B Red/Green/Blue. Video color analog DAC outputs. FB Fast Blanking. Video analog DAC output. VDD Main power supply voltage (5V10%, digital) WSCF, WSCR Analog pins for the VPS/WSS slicer . These pins must be tied to ground or not connected. VPP: On EPROM/OTP devices, the WSCR pin is replaced by VPP which is the programming voltage pin. VPP should be tied to GND in user mode. MCFM Analog pin for the display pixel frequency multiplier. OSCIN, OSCOUT Oscillator (input and output). These pins connect a parallel-resonant crystal (24MHz maximum), or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator inverter. Figure 3. 56-Pin Package Pin-Out
INT7/P2.0 RESET P0.7 P0.6 P0.5 P0.4 P0.3 AIN4/P0.2 P0.1 P0.0 CSO/RE SET0/P3.7 P3.6 P3.5 P3.4 B G R FB SDI/SDO/ P5.1 SCK/INT2/P5. 0 VDD JTDO WSCF VPP/WSCR AVDD3 TEST 0 MCFM JTCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity. HSYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to OSD. Positive or negative polarity. PXFM Analog pin for the Display Pixel Frequency Multiplier AVDD3 Analog V DD of PLL. This pin must be tied to VDD externally. GND Digital circuit ground. AGND Analog circuit ground (must be tied externally to digital GND). CVBS1 Composite video input signal for the Teletext slicer and sync extraction. CVBS2 Composite video input signal for the VPS/ WSS slicer. Pin AC coupled. AVDD1, AVDD2 Analog power supplies (must be tied externally to AVDD3). TXCF Analog pin for the Teletext slicer line PLL. CVBSO, JTDO, JTCK Test pins: leave floating. TEST0 Test pins: must be tied to AVDD2. JTRST0 Test pin: must be tied to GND.
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT P4.7/PWM7/EX TRG/ST OUT P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRSTO GND AGND CVBS1 CVBS2 JTMS AVDD2 CVBSO TXCF
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) Figure 4. ST92195B Required External components (56-pin package)
+5V P20 1F C2 R1 10k P07 P06 P05 P04 P03 P02 P01 P00 P37 P36 P35 P34 B G R FB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 U1 P2.0/INT7 RESETN P0.7 P0.6 P0.5 P0.4 P0.3 P0.2/AIN4 P0.1 P0.0 P3.7/RESET0/CSO P3.6 P3.5 P3.4 B G R FB P5.1/SDI/SDO P5.0/SCK/INT2 VDD JTDO WSCF WSCR AVDD3 TEST0 MCFM JTCK SDIP56 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6 /VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT P4.7/PWM7/EXTRG/STOUT P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3 /TSLU/HT P4.2/PWM2 ST92195B P4.1/PWM1 P4.0/PWM0 VSYNC HSY NC/CSYNC AVDD1 PXFM JTRST0 GND AGND CVBS1 CVBS2 JTMS AVDD2 CVBSO TXCF 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P21 P22 P23 P24 P25 C1 Y1 4Mhz C3 P47 P46 P45 P44 P43 P42 P41 P40 VSYNC H SYNC 82pF +5V 82pF
S1
D1 1N4148 L2 10uH
RST
L1 10uH
C4
10F
C5 100nF
C6
100nF
P51 P50
C7
10F
C8
22pF
C9
100 nF
R2
5.6k
C10
4.7nF
C11
22pF
C12
470nF CVBS
C13
4.7nF
R3
5.6k
C14
82pF
C15
100nF
R4
15k
C16
2.2nF
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) Figure 5. ST92195B Required External Components (64-pin package)
C1
1F
R1
10k
S1
D1 1N4148
+5V
RST
C2 C3 100nF L1 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 10uH C5 Y1 4Mhz C4
82pF
82pF
C6 U1 10uF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
100nF
P02 P01 P00 P37 P36 P35 P34 B G R FB C7 P5.0
1 2 3 4 5 6 7 8 9 10 11 12 P5.1 13 14 15 16
VSS P0.2/AIN4 P0.1 P0.0 P3.7/RESET0/CSO P3.6 P3.5 P3.4 B G R FB P5.1/SDI/SDO P5.0/SCK/INT2 VDD JTDO
VDD P0.3 P0.4 P0.5 P0.6 P0.7 RESETN INT7/P2.0 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT VDD
ST92195B
100nF
GND EXTRG/SLOUT/P4.7/PWM7 P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 HT/TSLU/P4.3/PWM3 P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC CSYNC/HSYNC AVDD1 PXFM JTRST0 GND NC
NC NC WSCF WSCR AVDD3 TEST0 MCFM JTCK TXCF CVBSO AVDD2 JTMS CVBS2 CVBS1 AGND NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P47 P46 P45 P44 P43 P42 P41 P40 VSYNC HSYNC C9 22pF
C8
100nF
R2 5.6k
C10 4.7nF
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
QFP64
C12 C11 100nF C14 C15 4.7nF 22pF R3 5.6k 100nF
C13 L2 10uF +5V 10uH
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0] I/O Port Lines (Input/Output, TTL or CMOS compatible). 28 lines grouped into I/O ports, bit programmable as general purpose I/O or as Alternate functions (see I/O section).
Important: Note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 I/O Port Alternate Functions. Each pin of the I/O ports of the ST92195B may assume software programmable Alternate Functions (see Table 1).
Table 1. ST92195B I/O Port Alternate Function Summary
Port Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 General Purpose I/O Pin No. TQFP64 SDIP56 4 3 2 63 62 61 60 59 57 56 10 9 8 7 6 5 4 3 1 56 INT7 AIN1 INT5 INT0 AIN2 INT6 VSO1 NMI AIN3 52 52 INT4 VSO2 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 8 7 6 5 40 41 42 14 13 12 11 42 43 44 RESET0 CSO PWM0 PWM1 PWM2 PWM3 P4.3 43 45 TSLU HT P4.4 44 46 PWM4 AIN4 I/O I/O I I/O I/O I/O I/O I/O I I I I I I O I I I O I/O I/O I/O O O O O O O O O O Internal Reset Output Composite Sync output PWM Output 0 PWM Output 1 PWM Output 2 PWM Output 3 Translucency Digital Output Half-tone Output PWM Output 4 External Interrupt 7 A/D Analog Data Input 1 External Interrupt 5 External Interrupt 0 A/D Analog Data Input 2 External Interrupt 6 Voltage Synthesis Output 1 Non Maskable Interrupt Input A/D Analog Data Input 3 External Interrupt 4 Voltage Synthesis Output 2 A/D Analog Data Input 4 Alternate Functions
P2.2
55
55
P2.3 P2.4
All ports useable for general purpose I/O (input, output or bidirectional)
54 53
54 53
P2.5
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ST92195B - GENERAL DESCRIPTION
Port Name P4.5 P4.6
General Purpose I/O
Pin No. TQFP64 SDIP56 45 46 47 48 PWM5 PWM6 EXTRG 47 49 PWM7 STOUT 14 20 INT2 SCK SDO SDI O O I O O I O O I
Alternate Functions PWM Output 5 PWM Output 6 A/D Converter External Trigger Input PWM Output 7 Standard Timer Output External Interrupt 2 SPI Serial Clock SPI Serial Data Out SPI Serial Data In
P4.7
P5.0
All ports useable for general purpose I/O (input, output or bidirectional)
P5.1
13
19
1.2.2 I/O Port Styles
Pins P0[7:0] P2[5,4,3,2] P2[1,0] P3.7 P3[6,5,4] P4[7:0] P5[1:0] Weak Pull-Up no no no yes no no no Port Style Standard I/O Standard I/O Schmitt trigger Standard I/O Standard I/O Standard I/O Standard I/O Reset Values BID / OD / TTL BID / OD / TTL BID / OD / TTL AF / PP / TTL BID / OD / TTL BID / OD / TTL BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table To configure the I/O ports, use the information in this table and the Port Bit Configuration Table in the I/O Ports Chapter of the datasheet. Port Style= the hardware characteristics fixed for each port line. Inputs: - If port style = Standard I/O, either TTL or CMOS input level can be selected by software. - If port style = Schmitt trigger, selecting CMOS or TTL input by software has no effect, the input will always be Schmitt Trigger. Weak Pull-Up = This column indicates if a weak pull-up is present or not.
- If WPU = yes, then the WPU can be enabled/disable by software - If WPU = no, then enabling the WPU by software has no effect Alternate Functions (AF) = More than one AF cannot be assigned to an external pin at the same time: An alternate function can be selected as follows. AF Inputs: - AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC analog inputs which must be explicitly selected as AF by software.
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) AF Outputs or Bidirectional Lines: - In the case of Outputs or I/Os, AF is selected explicitly by software. Example 1: ADC trigger digital input AF: EXTRG, Port: P4.7, Port Style: Standard I/O. Write the port configuration bits (for TTL level): P4C2.7=1 P4C1.7=0 P4C0.7=1 Enable the ADC trigger by software as described in the ADC chapter. Example 2: PWM 0 output AF: PWM0, Port: P4.0 Write the port configuration bits (for output pushpull): P4C2.0=0 P4C1.0=1 P4C0.0=1
Example 3: ADC analog input AF: AIN1, Port : P2.1, Port style: does not apply to analog inputs Write the port configuration bits: P2C2.1=1 P2C1.1=1 P2C0.1=1
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ST92195B - GENERAL DESCRIPTION
1.3 MEMORY MAP Internal ROM The ROM memory is mapped in a single continuous area starting at address 0000h in MMU segment 00h.
Device ST92195B1/B2/B3 ST92195B4/B5 ST92195B6 ST92195B7 Size 32K 48K 56K 64K Start Address 0000h 0000h 0000h 0000h End Address 7FFFh BFFFh DFFFh FFFFh ST92195B1 ST92195B2/B3/B4 ST92195B5/B6/B7 2K 6K 8K
Internal RAM, 256 bytes The internal RAM is mapped in MMU segment 20h; from address FF00h to FFFFh. Internal TDSRAM The Internal TDSRAM is mapped starting at address 8000h in MMU segment 22h. It is a fully static memory.
Device Size Start Address 8000h 8000h 8000h End Address 87FFh 97FFh 9FFFh
Figure 6. ST92195B Memory Map
229FFFh
max. 8 Kbytes TDSRAM
228000h
Reserved
22FFFFh 22C000h 22BFFFh 228000h 227FFFh
PAGE 91 - 16 Kbytes PAGE 90 - 16 Kbytes PAGE 89 - 16 Kbytes PAGE 88 - 16 Kbytes
SEGMENT 22h 64 Kbytes
Reserved
224000h 223FFFh
Reserved
220000h 21FFFFh
SEGMENT 21h 64 Kbytes
Reserved
Internal RAM 256 bytes
20FFFFh
210000h 20FFFFh
PAGE 83 - 16 Kbytes
20C000h 20BFFFh
20FF 00h
SEGMENT 20h 64 Kbytes
Reserved Reserved
PAGE 82 - 16 Kbytes
208000h 207FFFh
PAGE 81 - 16 Kbytes
204000h 203FFFh
Reserved
200000h 00FFFFh
PAGE 80 - 16 Kbytes
PAGE 3 - 16 Kbytes
00C000h 00BFFFh
SEGMENT 0 64 Kbytes
Internal ROM max. 64 Kbytes
PAGE 2 - 16 Kbytes
008000h 007FFFh
PAGE 1 - 16 Kbytes
004000h 003FFFh
PAGE 0 - 16 Kbytes
000000h
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ST92195B - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol V DD V SSA V DDA VI V AI VO TSTG IINJ Supply Voltage Analog Ground Analog Supply Voltage Input Voltage Analog Input Voltage (A/D Converter) Output Voltage Storage Temperature Pin Injected Current Maximum Accumulated Pin Injected Current In Device - 50 to +5 0 mA Parameter Value VSS - 0.3 to V SS + 7.0 VSS - 0.3 to V SS + 0.3 VDD -0.3 to VDD +0.3 VSS - 0.3 to V DD +0.3 VSS - 0.3 to V DD +0.3 VSSA - 0.3 to VDDA +0.3 VSS - 0.3 to V DD + 0.3 - 55 to + 150 - 5 to + 5 Unit V V V V V V C mA
Note: Stress above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD VDDA fOSCE fOSCI Operating Temperature Supply Voltage Analog Supply Voltage (PLL) External Oscillator Frequency Internal Clock Frequency (INTCLK) Parameter Value Min. 0 4.5 4.5 3.3 Max. 70 5.5 5.5 8.7 24 Unit C V V MHz MHz
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ST92195B - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified)
Symbol VIHCK VILCK VIH VIL VIH VIL VIHRS VILRS VHYRS VIHY VIHVH VILVH VHYHV VOH VOL IWPU ILKIO ILKRS ILKAD ILKOS Parameter Clock In high level Clock in low level Input high level Input low level Input high level Input low level Reset in high level Reset in low level Reset in hysteresis P2.(1:0) input hysteresis HSYNC/VSYNC input high level HSYNC/VSYNC input low level HSYNC/VSYNC input hysteresis Output high level Output low level Weak pull-up current I/O pin input leakage current Reset pin input A/D pin input leakage current OSCIN pin input leakage current Push-pull Ild=-0.8mA Push-pull ld=+1.6mA bidir. state VOL= 3V VOL= 7V 014/22
ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS PIN CAPACITANCE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified))
Symbol C IO Parameter Pin Capacitance Digital Input/Output Conditions Value min max 10 Unit pF
CURRENT CONSUMPTION (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified) Symbol IDD1 IDDA1 IDD2 IDDA2 Parameter Run Mode Current Run Mode Analog Current (pin VDDA ) HALT Mode Current HALT Mode Analog Current (pin VDDA ) Condition s notes 1,2; all On Timing Controller On notes 1,4 notes 1,4 Value min typ. 70 35 10 40 max 100 50 100 100 Unit mA mA A A
Notes: 1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor. The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode. 2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock. All peripherals working including Display. 3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock. The TDSRAM interface and the Slicers are working; the Display controller is not working. 4. VSYNC and HSYNC tied to VSS. External CLOCK pin (OSCIN) is hold low. All peripherals are disabled.
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode) (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified))
Symbol TwLR TwHR Parameter low level pulse width high level pulse width Conditions INTCLK=24 MHz. TpC+12 TpC+12 Value min 95 95 max ns ns Unit
TpC is the INTCLK clock period.
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ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont'd) SPI TIMING TABLE (VDD= 5V +/-10%; TA = 0 to 70C; Cload= 50pF)
Symbol TsDI ThDI TdOV ThDO TwSKL TwSKH Parameter Input Data Set-up Time Input Data Hold Time SCK to Output Data Valid Output Data Hold Time SCK Low Pulse Width SCK High Pulse Width tbd tbd tbd (1) OSCIN/2 as internal Clock Conditi on Value min tbd 1INTCLK +100ns tbd max Unit ns ns ns ns ns ns
(1) TpC is the OSCIN clock period; TpMC is the "Main Clock Frequency" period.
SKEW CORRECTOR TIMING TABLE (VDD= 5V +/-10%, TA = 0 to 70C, unless otherwise specified)
Symbol Tjskw Parameter Jitter on RGB output Conditions 36 MHz Skew corrector clock frequency max Value 5* Unit ns
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope of 100 fields
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ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont'd) OSD DAC CHARACTERISTICS (ROM DEVICES ONLY) (VDD= 5V +/-10%, TA = 0 to 70C, unless otherwise specified).
Symbol Parameter Output impedance: FB,R,G,B Output voltage: FB,R,G,B code= 111 code= 011 code= 000 FB= 1 FB= 0 Global voltage accuracy 2.4 0 Cload= 20pF RL = 100K 1.000 0.450 0.025 2.7 0.025 1.250 0.500 0.080 3.4 0.080 +/-5 V V V V V % Conditio ns Value min 300 typical 500 max 700 Unit Ohm
OSD DAC CHARACTERISTICS (EPROM AND OTP DEVICES ONLY) (VDD= 5V +/-10%, TA = 0 to 70C, unless otherwise specified).
Symbol Parameter Output impedance: FB,R,G,B Output voltage: FB,R,G,B code= 111 code= 011 code= 000 FB= 1 FB= 0 Global voltage accuracy VDD-0.8 0.400 +/-5 Cload= 20pF RL = 100K 1.100 0.600 0.200 1.400 0.800 0.350 V V V V V % Conditions Value min 300 typical 500 max 700 Unit Ohm
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ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont'd) A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified
Symbol Tlow Thigh Text Tstr Tlow Thigh Text Tstr Parameter Pulse Width Pulse Distance Period/fast Mode Start Conversion Delay Core Clock issued by Timing Controller Pulse Width Pulse Distance Period/fast Mode Start Conversion Delay ns ns s ns 78+1 INTCLK 0.5 1.5 OSCIN divide by 2;min/max OSCIN divide by 1; min/max Value min 1.5 INTCLK max Unit ns ns s INTCLK
A/D CONVERTER. ANALOG PARAMETERS TABLE (VDD= 5V +/-10%; TA = 0 to 70C; unless otherwise specified))
Parameter Analog Input Range Conversion Time Fast/Slow Sample Time Fast/Slow Power-up Time Resolution Differential Non Linearity Integral Non Linearity Absolute Accuracy Input Resistance Hold Capacitance
Notes: (*) (**) (1) (2) (3) (4)
Value typ (*) min VSS 78/138 51.5/87.5 60 8 1.5 2 2 2.5 3 3 1.5 1.92 max V DD
Unit (**) V INTCLK INTCLK s bits LSBs LSBs LSBs Kohm pF
Note
(1,2) (1)
(4) (4) (4) (3)
The values are expected at 25 Celsius degrees with VDD= 5V 'LSBs' , as used here, as a value of VDD/256 @ 24 MHz external clock including Sample time it must be considered as the on-chip series resistance before the sampling capacitor DNL ERROR= max {[V(i) -V(i-1)] / LSB-1} INL ERROR= max {[V(i) -V(0)] / LSB-i} ABSOLUTE ACCURACY= overall max conversion error
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ST92195B - GENERAL INFORMATION
3 GENERAL INFORMATION
3.1 PACKAGE MECHANICAL DATA Figure 7. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width
Dim. A A1 A2 b b2 C D E E1 e eA eB L PDIP56S N
mm Min 0.38 3.18 0.41 0.89 0.20 50.29 15.01 12.32 1.78 15.24 17.78 2.92 5.08 0.115 14.73 0.485 0.38 0.008 53.21 1.980 Typ Max 6.35 0.015 4.95 0.125 Min
inches Typ Max 0.250 0.195 0.016 0.035 0.015 2.095 0.591 0.580 0.070 0.600 0.700 0.200
Number of Pins 56
Figure 8. 64-Pin Thin Quad Flat Package
mm Min 0.05 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006
Dim A A1 A2 B C D D1 D3 E E1 E3 e K L L1 L1 L N K
1.35 1.40 1.45 0.053 0.055 0.057 0.30 0.37 0.45 0.012 0.015 0.018 0.09 16.00 14.00 12.00 16.00 14.00 12.00 0.80 0 3.5 1.00 64 ND 16 7 0.039 NE 16 0.20 0.004 0.630 0.551 0.472 0.630 0.551 0.472 0.031 0.008
0.45 0.60 0.75 0.018 0.024 0.030 Number of Pins
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ST92195B - GENERAL INFORMATION
PACKAGE MECHANICAL DATA (Cont'd) Figure 9. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width
Dim. A A1 B B1 C D D1 E1 e G G1 G2 G3 G4 0.76 0.38 0.76 0.23 0.46 0.89 0.25 48.01 1.78 mm Min Typ Max 4.17 0.030 0.56 0.015 0.018 0.022 1.02 0.030 0.035 0.040 0.38 0.009 0.010 0.015 1.890 0.070 Min inches Typ Max 0.164
50.04 50.80 51.56 1.970 2.000 2.030 14.48 14.99 15.49 0.570 0.590 0.610 14.12 14.38 14.63 0.556 0.566 0.576 18.69 18.95 19.20 0.736 0.746 0.756 1.14 0.045 11.05 11.30 11.56 0.435 0.445 0.455 15.11 15.37 15.62 0.595 0.605 0.615 2.92 1.40 56 5.08 0.115 0.055 Number of Pins 0.200
CDIP56SW
L S N
Figure 10. 64-Pin Ceramic Quad Flat Package
Dim A A1 B C D D1 D3 e G G2 L 0 CQFP064W N
mm Min Typ 0.50 Max 3.27 Min
inches Typ 0.020 Max 0.129
0.30 0.35 0.45 0.012 0.014 0.018 0.13 0.15 0.23 0.005 0.006 0.009 16.65 17.20 17.75 0.656 0.677 0.699 13.57 13.97 14.37 0.534 0.550 0.566 12.00 0.80 12.70 0.96 0.35 0.80 8.31 64 0.472 0.031 0.500 0.038 0.014 0.031 0.327
Number of Pins
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ST92195B - GENERAL INFORMATION
3.2 ORDERING INFORMATION Each device is available for production in a user programmable version (OTP) as well as in factory coded version (ROM). OTP devices are shipped to customer with a default blank content FFh, while ROM factory coded parts contain the code sent by customer. The common EPROM versions for debugging and prototyping features the maximum memory size and peripherals of the family. Care must be taken to only use resources available on the target device. Figure 11. ROM Factory Coded Device Types
TEMP. DEVICE PACKAGE RANGE / XXX
3.2.1 Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh.
Code name (defined by STMicroelectronics) 1= standard 0 to +70 C B= Plastic DIP56 T= Plastic TQFP64 ST92195B1 ST92195B2 ST92195B3 ST92195B4 ST92195B5 ST92195B6 ST92195B7
Figure 12. OTP User Programmable Device Types
DEVICE PACKAGE TEMP. RANGE / XXX
Code name (defined by STMicroelectronics) 1= 0 to +70 C B= Plastic DIP56 T= Plastic TQFP64 ST92T195B7
Figure 13. EPROM User Programmable Device Types
DEVICE PACKAGE TEMP. RANGE 0= 25 C B= Ceramic DIP 56 pin T= Ceramic QFP 64 pin ST92E195B7
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ST92195B - GENERAL INFORMATION
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2000 STMicroelectronics - All Rights Reserved. Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com
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